OpenLane
OpenLane
An automated RTL to GDSII flow for ASIC design.
OpenLane is a revolutionary open-source digital ASIC (Application-Specific Integrated Circuit) design flow. It completely automates the process of turning digital logic (RTL) into a physical silicon layout (GDSII).
Supported heavily by Google and the open-source hardware community, it integrates multiple open-source EDA tools into a seamless pipeline, dramatically lowering the barrier to entry for creating custom microchips.
Key Features
- Fully automated RTL-to-GDSII pipeline
- Integrates Yosys, OpenROAD, and Magic
- Optimized for open-source PDKs (Skywater 130nm, GF180MCU)
- Highly configurable architecture exploration
- Dockerized for easy installation
Frequently Asked Questions
Yes, OpenLane is open source. It is released under the Apache-2.0 license.
You can use OpenLane as a free, open-source alternative to Synopsys Design Compiler.
Yes, OpenLane can be self-hosted on your own server or cloud infrastructure.
It is built using Python, Dockerfile, Makefile, Tcl, Verilog.
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